US 12,224,311 B1
Power MOSFET with gate-source ESD diode structure
Wan-Yu Kai, New Taipei (TW); Chia-Wei Hu, New Taipei (TW); and Ta-Chuan Kuo, New Taipei (TW)
Assigned to Diodes Incorporated, Plano, TX (US)
Filed by Diodes Incorporated, Plano, TX (US)
Filed on Jun. 18, 2024, as Appl. No. 18/747,341.
Application 18/747,341 is a division of application No. 18/416,776, filed on Jan. 18, 2024, granted, now 12,154,941.
Int. Cl. H01L 29/861 (2006.01); H01L 27/02 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01); H01L 29/78 (2006.01)
CPC H01L 29/063 (2013.01) [H01L 27/0255 (2013.01); H01L 29/4236 (2013.01); H01L 29/7813 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a drain and a source on opposing sides of an epitaxial layer;
a plurality of gates formed in the epitaxial layer;
a source contact connected to the source;
a gate contact connected to the plurality of gates;
a drain contact on opposing sides of the epitaxial layer of the source contact;
a gate-source Electrostatic Discharge (ESD) diode structure connected between the gate contact and the source contact, wherein the gate-source ESD diode structure comprises a first n+ region;
a breakdown voltage enhancement and leakage prevention structure formed underneath the gate-source ESD diode structure; and
wherein the breakdown voltage enhancement and leakage prevention structure comprises a body ring structure, wherein the body ring structure comprises a plurality of rectangles:
in a cross-sectional view, the plurality of rectangles of the body ring structure comprises at least a first column and a second column, with one sidewall of the first column vertically aligned with a first sidewall of the first n+ region and one sidewall of the second column vertically aligned with a second sidewall of the first n+ region, respectively.