US 12,224,310 B2
Single-crystal transistors for memory devices
Fatma Arzum Simsek-Ege, Boise, ID (US); Masihhur R. Laskar, Meridian, ID (US); Nicholas R. Tapias, Boise, ID (US); Darwin Franseda Fan, Boise, ID (US); and Manuj Nahar, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Dec. 6, 2023, as Appl. No. 18/531,525.
Application 18/531,525 is a division of application No. 17/366,557, filed on Jul. 2, 2021, granted, now 11,862,668.
Prior Publication US 2024/0105766 A1, Mar. 28, 2024
Int. Cl. H01L 29/10 (2006.01); H01L 29/04 (2006.01); H10B 12/00 (2023.01); H10B 53/30 (2023.01)
CPC H01L 29/04 (2013.01) [H01L 29/1033 (2013.01); H10B 12/00 (2023.02); H10B 53/30 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An apparatus, comprising:
a dielectric portion;
a semiconductor portion in contact with a top surface of the dielectric portion and extending into the dielectric portion with a tapered projection, the semiconductor portion comprising a single-grain crystalline arrangement;
a first transistor terminal in contact with a top surface of the semiconductor portion at a first location;
a second transistor terminal in contact with the top surface of the semiconductor portion at a second location;
a transistor gate dielectric in contact with the top surface of the semiconductor portion at a third location between the first location and the second location; and
a transistor gate conductor in contact with a top surface of the transistor gate dielectric.