| CPC H01L 27/14636 (2013.01) [H01L 27/1463 (2013.01); H01L 27/1464 (2013.01); H01L 27/14645 (2013.01); H01L 27/14689 (2013.01)] | 20 Claims |
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1. A method for forming an integrated circuit (IC) chip, the method comprising:
forming a trench isolation structure extending into a frontside of a substrate;
forming a semiconductor device on the frontside;
forming an interconnect structure overlying the trench isolation structure and the semiconductor device on the frontside, and comprising a device wire, a contact via extending from the device wire to the semiconductor device, a first bond wire farther from the substrate than the device wire, a second bond wire overlying the first bond wire and farther from the substrate than the first bond wire, and a plurality of bond vias extending vertically in a dimension orthogonal to a surface of the first bond wire, from contact with the first bond wire to contact with the second bond wire; and
forming a pad structure from a backside of the substrate, opposite the frontside, wherein the pad structure has a pair of protrusions extending through the trench isolation structure to contact with the surface of the first bond wire;
wherein a top layout of the first or second bond wire has a first area, wherein a top layout of the plurality of bond vias has a second area that is 10% or more of the first area, wherein the plurality of bond vias are spaced from each other and comprise a central bond via and a pair of peripheral bond vias, wherein the central bond via is in a plane that is orthogonal to the dimension and that is between and spaced from the first and second bond wires, and wherein the pair of peripheral bond vias extend in individual, continuous closed paths around the central bond via in the plane.
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