US 12,224,289 B2
Array substrate including non-overlapping line segments and gate lines and manufacturing method therefor, and display device
Ning Liu, Beijing (CN); Wei Song, Beijing (CN); Yingbin Hu, Beijing (CN); Qinghe Wang, Beijing (CN); Feng Zhang, Beijing (CN); Chongchong Liu, Beijing (CN); and Bin Zhou, Beijing (CN)
Assigned to HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., Anhui (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
Appl. No. 17/283,425
Filed by HEFEI XINSHENG OPTOELECTRONICS TECHNOLOGY CO., LTD., Anhui (CN); and BOE TECHNOLOGY GROUP CO., LTD., Beijing (CN)
PCT Filed Jun. 19, 2020, PCT No. PCT/CN2020/097025
§ 371(c)(1), (2) Date Apr. 7, 2021,
PCT Pub. No. WO2020/253813, PCT Pub. Date Dec. 24, 2020.
Claims priority of application No. 201910536367.8 (CN), filed on Jun. 20, 2019.
Prior Publication US 2021/0343757 A1, Nov. 4, 2021
Int. Cl. H01L 27/12 (2006.01); H01L 29/786 (2006.01)
CPC H01L 27/1244 (2013.01) [H01L 27/1248 (2013.01); H01L 27/1251 (2013.01); H01L 27/127 (2013.01); H01L 29/78666 (2013.01); H01L 29/78672 (2013.01)] 13 Claims
OG exemplary drawing
 
1. An array substrate, comprising:
a base, having a plurality of sub-pixel regions;
a plurality of gate lines and a plurality of data lines disposed on the base, wherein the plurality of data lines all extend in a first direction, and the plurality of gate lines all extend in a second direction, the first direction intersecting the second direction;
at least one of the plurality of data lines includes a plurality of first line segments and a plurality of second line segments that all extend in the first direction, the plurality of first lines segments and the plurality of second line segments being arranged alternately;
the plurality of second line segments are disposed at a side of the plurality of gate lines proximate to the base, and the plurality of first line segments are disposed at a side of the plurality of gate lines away from the base; and
orthographic projections of the plurality of first line segments on the base are non-overlapping with orthographic projections of the plurality of gate lines on the base;
an insulating layer disposed between the plurality of first line segments and the plurality of second line segments, the insulating layer including a plurality of first vias, wherein in the first direction, any two adjacent first line segments are electrically connected to a second line segment located between the two adjacent first line segments through at least two first vias; and
a plurality of pixel circuits disposed on the base, each pixel circuit being disposed in a sub-pixel region, and the pixel circuit being electrically connected to a gate line and a data line, wherein the pixel circuit includes a first switching transistor, a first gate of the first switching transistor and the gate line being disposed in a same layer and made of a same material, and a first source and a first drain of the first switching transistor and the plurality of first line segments being disposed in a same layer and made of a same material.