US 12,224,281 B2
Interdigitated device stack
Lars Liebmann, Mechanicsville, NY (US); Jeffrey Smith, Clifton Park, NY (US); Daniel Chanemougame, Niskayuna, NY (US); Paul Gutwin, Williston, VT (US); Brian Cline, Austin, TX (US); Xiaoqing Xu, Austin, TX (US); and David Pietromonaco, San Jose, CA (US)
Assigned to TOKYO ELECTRON LIMITED, Tokyo (JP)
Filed by TOKYO ELECTRON LIMITED, Tokyo (JP)
Filed on Dec. 3, 2021, as Appl. No. 17/541,609.
Claims priority of provisional application 63/121,846, filed on Dec. 4, 2020.
Prior Publication US 2022/0181318 A1, Jun. 9, 2022
Int. Cl. H01L 27/06 (2006.01); H01L 27/092 (2006.01)
CPC H01L 27/0688 (2013.01) [H01L 27/092 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a first pair of transistors positioned over a substrate, the first pair of transistors including a first transistor that has a first gate structure and is positioned over the substrate and a second transistor that has a second gate structure and is stacked over the first transistor; and
a second pair of transistors stacked over the first pair of transistors, resulting in a vertical stack perpendicular to a working surface of the substrate, the second pair of transistors including a third transistor that has a third gate structure and is stacked over the second transistor and a fourth transistor that has a fourth gate structure and is stacked over the third transistor, wherein
the third gate structure extends from a central region of the vertical stack to a first side of the vertical stack,
the second gate structure and the fourth gate structure both extend from the central region of the vertical stack to a second side of the vertical stack opposite the first side of the vertical stack, and
the first gate structure, the second gate structure, the third gate structure and the fourth gate structure are spaced apart from one another.