US 12,224,277 B2
Memory devices having cell over periphery structure, memory packages including the same, and methods of manufacturing the same
Yonghyuk Choi, Suwon-si (KR); Bongsoon Lim, Seoul (KR); Hongsoo Jeon, Suwon-si (KR); and Jaeduk Yu, Seoul (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-Do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Jan. 3, 2023, as Appl. No. 18/149,206.
Application 18/149,206 is a continuation of application No. 17/026,637, filed on Sep. 21, 2020, granted, now 11,581,297.
Claims priority of application No. 10-2019-0175917 (KR), filed on Dec. 27, 2019.
Prior Publication US 2023/0140959 A1, May 11, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 23/528 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); H01L 23/00 (2006.01); H01L 25/065 (2023.01); H01L 25/07 (2006.01); H01L 25/18 (2023.01); H01L 27/112 (2006.01)
CPC H01L 25/18 (2013.01) [G11C 16/0483 (2013.01); G11C 16/08 (2013.01); H01L 24/05 (2013.01); H01L 24/08 (2013.01); H01L 25/0657 (2013.01); H01L 2224/05147 (2013.01); H01L 2224/08145 (2013.01); H01L 2924/1431 (2013.01); H01L 2924/14511 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a first semiconductor layer including a plurality of wordlines extending in a first direction and a plurality of bitlines extending in a second direction that is perpendicular to the first direction, the first semiconductor layer further including
an upper substrate, and
a memory cell array on the upper substrate and including a first memory block; and
a second semiconductor layer beneath the first semiconductor layer in a third direction, the third direction perpendicular to both the first direction and the second direction, the second semiconductor layer including
a lower substrate, and
an address decoder on the lower substrate and configured to control the memory cell array,
wherein the first memory block includes
a first core region including first memory cells, and
a first extension region adjacent to a first side of the first core region, the first extension region including an insulating mold structure,
wherein the first extension region includes
a plurality of step zones having a step shape in a cross-sectional view, and
at least one flat zone having a flat shape in the cross-sectional view,
wherein the memory device further includes a plurality of through-hole vias penetrating the insulating mold structure in the at least one flat zone,
wherein the plurality of wordlines and the address decoder are electrically connected to each other by at least the plurality of through-hole vias, and
wherein a quantity of step zones in the first extension region is equal to a quantity of flat zones in the first extension region.