US 12,224,267 B2
Chip interconnecting method, interconnect device and method for forming chip packages
Weiping Li, Shanghai (CN)
Assigned to Yibu Semiconductor Co., Ltd., Shanghai (CN)
Filed by Yibu Semiconductor Co., Ltd., Shanghai (CN)
Filed on Dec. 4, 2021, as Appl. No. 17/542,417.
Claims priority of application No. 202011408981.5 (CN), filed on Dec. 4, 2020; application No. 202011411137.8 (CN), filed on Dec. 4, 2020; and application No. 202011412884.3 (CN), filed on Dec. 4, 2020.
Prior Publication US 2022/0181297 A1, Jun. 9, 2022
Int. Cl. H01L 25/065 (2023.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/48 (2006.01); H01L 23/498 (2006.01)
CPC H01L 25/0655 (2013.01) [H01L 21/486 (2013.01); H01L 21/561 (2013.01); H01L 21/568 (2013.01); H01L 23/3107 (2013.01); H01L 23/481 (2013.01); H01L 23/49827 (2013.01); H01L 23/4985 (2013.01); H01L 24/16 (2013.01); H01L 24/48 (2013.01); H01L 24/73 (2013.01); H01L 24/81 (2013.01); H01L 24/82 (2013.01); H01L 24/95 (2013.01); H01L 24/96 (2013.01); H01L 2224/16157 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/81143 (2013.01); H01L 2224/81203 (2013.01); H01L 2224/8212 (2013.01); H01L 2224/82203 (2013.01); H01L 2224/95001 (2013.01); H01L 2924/10253 (2013.01); H01L 2924/10272 (2013.01); H01L 2924/10329 (2013.01); H01L 2924/1033 (2013.01); H01L 2924/15311 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A method of chip interconnection, comprising:
arranging at least one chipset on a surface of a carrier, each chipset including at least a first chip and a second chip, the first chip including first bumps formed on a first portion of a front surface of the first chip, the second chip including second bumps formed on a first portion of a front surface of the second chip, wherein the first bumps include a plurality of first bumps having a first density and the second bumps include a plurality of second bumps having a second density, the first density being higher than the second density; and
attaching an interconnect device to the first portion of the front surface of the first chip and to the first portion of the front surface of the second chip, the interconnect device having a first side and a plurality pads formed on the first side, the plurality of pads including a plurality of first pads for respectively bonding to the plurality of first bumps having the first density on the first chip and a plurality of second pads for respectively bonding to the plurality of second bumps having the second density on the second chip, wherein attaching the interconnect device includes:
aligning and bonding the plurality of first pads with respective ones of the plurality of first bumps having the first density on the first chip; and
after a placement position of the interconnect device is fixed due to the plurality of first pads being respectively bonded with respective ones of the plurality of first bumps, bonding the plurality of second pads to respective ones of the plurality of second bumps having the second density on the second chip by self-alignment bonding.