US 12,224,266 B2
Semiconductor packages including passive devices and methods of forming same
Shin-Puu Jeng, Hsinchu (TW); Po-Yao Chuang, Hsinchu (TW); and Shuo-Mao Chen, New Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Nov. 3, 2023, as Appl. No. 18/501,314.
Application 18/501,314 is a continuation of application No. 17/688,448, filed on Mar. 7, 2022, granted, now 11,848,305.
Application 17/688,448 is a continuation of application No. 16/934,861, filed on Jul. 21, 2020, granted, now 11,270,975, issued on Mar. 8, 2022.
Prior Publication US 2024/0063182 A1, Feb. 22, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 25/065 (2023.01); H01L 21/56 (2006.01); H01L 23/31 (2006.01); H01L 23/538 (2006.01); H01L 25/00 (2006.01)
CPC H01L 25/0652 (2013.01) [H01L 21/568 (2013.01); H01L 23/3128 (2013.01); H01L 23/3135 (2013.01); H01L 23/5383 (2013.01); H01L 23/5385 (2013.01); H01L 25/50 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A structure comprising:
a stack of semiconductor devices, each of the semiconductor devices comprising:
trench capacitors on a substrate; and
through vias extending through the substrate, the through vias being electrically coupled to the trench capacitors;
first conductive connectors between each of the semiconductor devices of the stack of semiconductor devices, the first conductive connectors mechanically and electrically bonding the adjacent semiconductor devices together;
underfill between the adjacent semiconductor devices and surrounding the first conductive connectors;
a first encapsulant on sidewalls of the stack of semiconductor devices and the underfill; and
second conductive connectors electrically coupled to a lowermost semiconductor device of the stack of semiconductor devices, the second conductive connectors being on an opposite side of the lowermost semiconductor device as the first conductive connectors.