| CPC H01L 24/20 (2013.01) [H01L 23/49816 (2013.01); H01L 23/49827 (2013.01); H01L 24/16 (2013.01); H01L 25/105 (2013.01); H01L 2224/16227 (2013.01); H01L 2224/211 (2013.01); H01L 2225/107 (2013.01)] | 18 Claims |
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1. A semiconductor package comprising:
a plurality of lower pads;
a plurality of upper pads;
a semiconductor chip including a chip pad and configured to transmit a first signal through the chip pad to a memory chip included in a memory package or receive the first signal through the chip pad from the memory chip included in the memory package;
a first wiring structure connecting the chip pad to a first lower pad among the plurality of lower pads; and
a plurality of second wiring structures connecting a plurality of second lower pads among the plurality of lower pads to the plurality of upper pads, the plurality of second wiring structures respectively including a plurality of conductive connectors that face side surfaces of the semiconductor chip,
a first external connection terminal connected to the first lower pad; and
a plurality of second external connection terminals respectively connected to the plurality of second lower pads,
wherein the first lower pad and one of the plurality of second lower pads are separated from each other by a minimum distance between the plurality of lower pads,
wherein when the semiconductor package and the memory package are horizontally mounted on a substrate base, the first wiring structure and the plurality of second wiring structures are electrically separated, the first external connection terminal is connected to a wiring structure transferring the first signal is formed in the substrate base, the plurality of second external connection terminals are electrically separated to the wiring structure, the semiconductor chip is laterally disposed between the plurality of conductive connectors, and none of the plurality of conductive connectors are electrically connected to the semiconductor chip.
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