US 12,224,258 B2
Semiconductor chip and semiconductor package including the same
Wonkyun Kwon, Osan-si (KR); and Chulyong Jang, Anyang-si (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Oct. 16, 2023, as Appl. No. 18/380,404.
Application 18/380,404 is a continuation of application No. 17/465,964, filed on Sep. 3, 2021, granted, now 11,824,023.
Claims priority of application No. 10-2021-0005390 (KR), filed on Jan. 14, 2021.
Prior Publication US 2024/0038699 A1, Feb. 1, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/768 (2006.01); H01L 23/00 (2006.01); H01L 23/48 (2006.01); H01L 25/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 24/05 (2013.01) [H01L 21/76871 (2013.01); H01L 23/481 (2013.01); H01L 24/73 (2013.01); H01L 24/83 (2013.01); H01L 25/0657 (2013.01); H01L 25/50 (2013.01); H01L 2224/023 (2013.01); H01L 2224/0401 (2013.01); H01L 2224/05025 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor chip comprising:
a semiconductor substrate having a first surface and a second surface opposite to the first surface, and an active layer disposed in a portion of the semiconductor substrate that is adjacent to the first surface;
a through electrode extending in the semiconductor substrate in a vertical direction, the through electrode having a lower surface extending partially through the semiconductor substrate and directly connected to the active layer and an upper surface positioned at a level lower than a level of the second surface of the semiconductor substrate;
a passivation layer disposed on the second surface of the semiconductor substrate; and
a bonding pad arranged on a portion of the passivation layer and the upper surface of the through electrode, the bonding pad having a cross-section with a “T” shape in the vertical direction, the bonding pad is connected to the through electrode.