US 12,224,257 B2
Semiconductor structure and manufacturing method thereof
Ming-Fa Chen, Taichung (TW); Hsien-Wei Chen, Hsinchu (TW); and Jie Chen, New Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 3, 2022, as Appl. No. 17/857,026.
Application 17/857,026 is a division of application No. 16/919,068, filed on Jul. 1, 2020, granted, now 11,410,948.
Claims priority of provisional application 62/905,412, filed on Sep. 25, 2019.
Prior Publication US 2022/0336392 A1, Oct. 20, 2022
Int. Cl. H01L 23/31 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01)
CPC H01L 24/05 (2013.01) [H01L 21/56 (2013.01); H01L 23/3121 (2013.01); H01L 24/03 (2013.01); H01L 24/29 (2013.01); H01L 2224/02371 (2013.01); H01L 2924/3511 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
an encapsulated integrated circuit (IC) component;
a redistribution structure overlying and bonded to the encapsulated IC component, wherein a bonding interface of the redistribution structure and the encapsulated IC component is substantially flat; and
a warpage control portion underlying the encapsulated IC component and comprising:
a first substrate;
a first patterned dielectric layer disposed between the first substrate and the encapsulated IC component, wherein sidewalls of the first substrate and the first patterned dielectric layer are coterminous with sidewalls of the encapsulated IC component and the redistribution structure; and
a first metal pattern laterally covered by the first patterned dielectric layer and electrically floating in the warpage control portion.