US 12,224,256 B2
Wafer structure and semiconductor device
Hyunsu Hwang, Siheung-si (KR); Junyun Kweon, Cheonan-si (KR); Jumyong Park, Cheonan-si (KR); Solji Song, Suwon-si (KR); Dongjoon Oh, Suwon-si (KR); and Chungsun Lee, Asan-si (KR)
Assigned to Samsung Electronics Co., Ltd., Gyeonggi-do (KR)
Filed by Samsung Electronics Co., Ltd., Suwon-si (KR)
Filed on Apr. 1, 2022, as Appl. No. 17/711,370.
Claims priority of application No. 10-2021-0117875 (KR), filed on Sep. 3, 2021.
Prior Publication US 2023/0073690 A1, Mar. 9, 2023
Int. Cl. H01L 23/00 (2006.01); H01L 23/522 (2006.01); H01L 23/544 (2006.01)
CPC H01L 24/05 (2013.01) [H01L 23/5226 (2013.01); H01L 23/544 (2013.01); H01L 23/562 (2013.01); H01L 2223/54426 (2013.01); H01L 2224/0557 (2013.01); H01L 2224/05582 (2013.01); H01L 2924/37001 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A wafer structure, comprising:
a semiconductor substrate that includes a chip region and a scribe lane region;
a first dielectric layer on a first surface of the semiconductor substrate;
a second dielectric layer on the first dielectric layer;
a dielectric pattern between the first dielectric layer and the second dielectric layer;
a through via that penetrates the first surface and a second surface at the chip region of the semiconductor substrate; and
a conductive pad in the second dielectric layer and on the through via,
wherein the dielectric pattern includes:
an etch stop pattern on the chip region of the semiconductor substrate and in contact with a bottom surface of the conductive pad; and
an alignment key pattern on the scribe lane region of the semiconductor substrate.