US 12,224,253 B2
Magnetic inductor device and method
Xin Ning, Tigard, OR (US); Brandon C. Marin, Gilbert, AZ (US); Kyu Oh Lee, Chandler, AZ (US); Siddharth K. Alur, Chandler, AZ (US); Numair Ahmed, Chandler, AZ (US); Brent Williams, Chandler, AZ (US); Mollie Stewart, Scottsdale, AZ (US); Nathan Ou, Chandler, AZ (US); and Cary Kuliasha, Mesa, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Sep. 20, 2021, as Appl. No. 17/480,064.
Prior Publication US 2023/0092492 A1, Mar. 23, 2023
Int. Cl. H01L 23/64 (2006.01); H01F 27/28 (2006.01); H01L 21/48 (2006.01); H01L 23/498 (2006.01); H01L 49/02 (2006.01)
CPC H01L 23/645 (2013.01) [H01F 27/2804 (2013.01); H01L 21/486 (2013.01); H01L 23/49827 (2013.01); H01L 23/49866 (2013.01); H01L 28/10 (2013.01)] 27 Claims
OG exemplary drawing
 
1. A semiconductor substrate comprising:
a core;
a dielectric layer fixed on the core;
at least one first electrical transmission pathway extending through at least one of the dielectric layer and the core, including:
a magnetic material disposed within the at least the core of the at least one first electrical transmission pathway;
at least one second electrical transmission pathway extending through the magnetic material;
a nickel layer disposed on inner circumferential surface of the magnetic material at least within the second electrical transmission pathway;
a copper layer disposed on at least the dielectric layer within the second electrical transmission pathway, wherein:
the dielectric layer or the nickel layer separates the copper layer from the magnetic material; and
at least one third pathway extending through at least one of the dielectric layer and the core separate from the at least one electrical transmission pathway.