US 12,224,246 B2
Flexible hybrid electronic system processing method and flexible hybrid electronic system
Wei Wang, Beijing (CN); and Lang Chen, Beijing (CN)
Assigned to PEKING UNIVERSITY, Beijing (CN)
Appl. No. 17/763,217
Filed by PEKING UNIVERSITY, Beijing (CN)
PCT Filed Apr. 30, 2021, PCT No. PCT/CN2021/091483
§ 371(c)(1), (2) Date Mar. 24, 2022,
PCT Pub. No. WO2022/183584, PCT Pub. Date Sep. 9, 2022.
Claims priority of application No. 202110224990.7 (CN), filed on Mar. 1, 2021.
Prior Publication US 2023/0170307 A1, Jun. 1, 2023
Int. Cl. H01L 23/538 (2006.01); H01L 21/48 (2006.01); H01L 21/56 (2006.01); H01L 23/00 (2006.01)
CPC H01L 23/5387 (2013.01) [H01L 21/481 (2013.01); H01L 21/568 (2013.01); H01L 24/83 (2013.01); H01L 2224/83203 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A processing method of a flexible hybrid electronic system, comprising:
step 1: etching out embedded grooves on a front surface of a silicon-based substrate, wherein a size of each of the embedded grooves is consistent with a size of a corresponding chip of a plurality of chips;
step 2: by using chip adhesive glues or chip adhesive films, embedding and gluing the plurality of chips into the embedded grooves, wherein front surfaces of the plurality of chips embedded are flush or nearly flush with the front surface of the silicon-based substrate;
step 3: etching and filling first polymers on a front surface of a silicon-connection structure between each of the plurality of chips embedded, to obtain a structure filled with the first polymers and realize flexible connections among the plurality of chips, wherein the silicon-connection structure is a silicon-based substrate between each of the plurality of chips embedded;
step 4: polishing surfaces of the structure filled with the first polymers, to obtain flat surfaces of the structure filled with the first polymers;
step 5: obtaining a metal wire between each of the plurality of chips from the flat surfaces of the structure filled with the first polymers, to obtain a structures completing the electrical interconnection and realize an electrical interconnection between each of the plurality of chips;
step 6: covering second polymers on surfaces of the structure completing the electrical interconnection, to obtain a structure completing the insulation protection and realize an insulation protection of the electrical interconnection;
step 7: thinning from back surface of the structure completing the insulation protection until the chip adhesive glues or the chip adhesive films of the plurality of chips are exposed, to obtain a structure thinned; and
step 8: covering third polymers on the back surface of the structure thinned, to perform a flexible protection.