US 12,224,245 B2
Embedded die architecture and method of making
Sanka Ganesan, Chandler, AZ (US); Robert L. Sankman, Phoenix, AZ (US); and Sri Chaitra Jyotsna Chavali, Chandler, AZ (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 23, 2019, as Appl. No. 16/724,907.
Prior Publication US 2021/0193579 A1, Jun. 24, 2021
Int. Cl. H01L 23/538 (2006.01); H01L 21/768 (2006.01); H01L 23/498 (2006.01)
CPC H01L 23/5384 (2013.01) [H01L 21/76802 (2013.01); H01L 23/49816 (2013.01); H01L 23/5381 (2013.01); H01L 23/5386 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a core comprising a glass;
a substrate, comprising:
embedded components comprising one or more semiconductor materials, and one or more insulating layers;
a first die comprising a plurality of vias extending from one surface of the first die to an opposite surface of the first die, wherein a first portion of the substrate is between the core and the first die, and the core is between a second portion of the substrate and the first portion of the substrate;
a second die over a first portion of the first die and coupled to a first via of the plurality of vias of the first die;
a third die over a second portion of the first die and coupled to a second via of the plurality of vias of the first die;
a third via extending through an entire thickness of the core and an entire thickness of the substrate; and
a fourth via extending through the entire thickness of the core and the entire thickness of the substrate,
wherein the third via is coupled to the first via, and the fourth via is coupled to the second via.