US 12,224,242 B2
Semiconductor memory device
Natsuki Iijima, Yokkaichi (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Dec. 8, 2021, as Appl. No. 17/643,285.
Claims priority of application No. 2021-098827 (JP), filed on Jun. 14, 2021.
Prior Publication US 2022/0399274 A1, Dec. 15, 2022
Int. Cl. H01L 23/535 (2006.01); H01L 23/522 (2006.01); H01L 23/528 (2006.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01)
CPC H01L 23/535 (2013.01) [H01L 23/5226 (2013.01); H01L 23/5283 (2013.01); H10B 41/27 (2023.02); H10B 43/27 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a first conductive layer;
a stacked body including a plurality of second conductive layers and a plurality of first insulating layers alternately stacked one by one above the first conductive layer, and including a stepped portion in which the plurality of second conductive layers is terraced;
a plurality of first pillars arranged in a memory region that is away from the stepped portion in a first direction that crosses a stacking direction of the stacked body, each first pillar including a semiconductor layer that penetrates the stacked body and connects with the first conductive layer, and forming a memory cell at an intersection with at least a part of the plurality of second conductive layers; and
a plate-like portion including a third conductive layer that extends in the stacked body from the stepped portion to the memory region continuously in the stacking direction and in the first direction, the plate-like portion dividing the stacked body in a second direction that crosses both the stacking direction and the first direction, wherein
the plate-like portion includes, in the stepped portion, a plurality of contact portions that is arranged intermittently in the first direction, the plurality of contact portions penetrating the stacked body and connecting with the first conductive layer.