US 12,224,241 B2
Semiconductor device and manufacturing method thereof including a conductive-material etching process to further adjust a via shape
Shih-Ming Chang, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Apr. 20, 2022, as Appl. No. 17/725,300.
Claims priority of provisional application 63/282,035, filed on Nov. 22, 2021.
Prior Publication US 2023/0163071 A1, May 25, 2023
Int. Cl. H01L 23/528 (2006.01); H01L 21/768 (2006.01); H01L 23/522 (2006.01); H01L 23/535 (2006.01)
CPC H01L 23/5283 (2013.01) [H01L 21/76805 (2013.01); H01L 21/76895 (2013.01); H01L 23/5226 (2013.01); H01L 23/535 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device comprising:
forming a first conductive pattern in a first interlayer dielectric (ILD) layer disposed over a substrate;
forming a second ILD layer over the first conductive pattern and the first ILD layer;
forming a via contact in the second ILD layer to contact an upper surface of the first conductive pattern;
forming a second conductive pattern over the via contact wherein a part of an upper surface of the via contact is exposed from the second conductive pattern in plan view;
etching the part of the upper surface of the via contact by using the second conductive pattern as an etching mask, thereby forming a space between the via contact and the second ILD layer; and
forming a third ILD layer over the second ILD layer.
 
11. A method of manufacturing a semiconductor device comprising:
forming a first conductive pattern in a first interlayer dielectric (ILD) layer disposed over a substrate;
forming a second ILD layer over the first conductive pattern and the first ILD layer;
forming a via contact in the second ILD layer to contact an upper surface of the first conductive pattern;
forming a second conductive pattern over the via contact wherein a part of an upper surface of the via contact is exposed from the second conductive pattern at both sides of the second conductive pattern in plan view;
etching the part of the via contact, thereby forming spaces between the via contact and the second ILD layer; and
forming a third ILD layer over the second ILD layer, wherein:
the second conductive pattern is formed by etching using a hard mask pattern as an etching mask, and
the part of the via contact is etched by using the hard mask pattern as an etching mask.
 
17. A method of manufacturing a semiconductor device comprising:
forming a first conductive pattern in a first interlayer dielectric (ILD) layer disposed over a substrate;
forming a second ILD layer over the first conductive pattern and the first ILD layer;
forming a via contact in the second ILD layer to contact an upper surface of the first conductive pattern;
forming a second conductive pattern over the via contact wherein a part of an upper surface of the via contact is exposed from the second conductive pattern in plan view;
etching the second ILD layer to expose at least a part of a side face of the via contact;
etching the part of the upper surface of the via contact by using the second conductive pattern as an etching mask; and
forming a third ILD layer over the second ILD layer.