US 12,224,239 B2
Internal node jumper for memory bit cells
Smita Shridharan, Beaverton, OR (US); Zheng Guo, Portland, OR (US); Eric A. Karl, Portland, OR (US); George Shchupak, Zviya (IL); and Tali Kosinovsky, Haifa (IL)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 7, 2024, as Appl. No. 18/599,049.
Application 18/599,049 is a continuation of application No. 18/119,225, filed on Mar. 8, 2023, granted, now 11,973,032.
Application 18/119,225 is a continuation of application No. 17/524,665, filed on Nov. 11, 2021, granted, now 11,640,939, issued on May 2, 2023.
Application 17/524,665 is a continuation of application No. 16/604,807, granted, now 11,205,616, issued on Dec. 21, 2021, previously published as PCT/US2017/038389, filed on Jun. 20, 2017.
Prior Publication US 2024/0213154 A1, Jun. 27, 2024
Int. Cl. H01L 23/528 (2006.01); H01L 23/535 (2006.01); H01L 27/092 (2006.01); H10B 10/00 (2023.01)
CPC H01L 23/528 (2013.01) [H01L 23/535 (2013.01); H01L 27/0924 (2013.01); H10B 10/12 (2023.02)] 20 Claims
OG exemplary drawing
 
1. An integrated circuit structure, comprising:
a fin along a first direction;
a first metal line, a second metal line and a third metal line along a second direction, the second direction orthogonal to the first direction, wherein the first metal line, the second metal line and the third metal line are within a footprint vertically over the fin; and
a first gate electrode and a second gate electrode along the second direction, the first gate electrode and the second gate electrode vertically over the fin and below the first metal line, the second metal line and the third metal line, wherein the first gate electrode and the second gate electrode but no additional gate electrodes are within the footprint of the first metal line, the second metal line and the third metal line.