US 12,224,237 B2
Method of manufacturing a via and a metal wiring for a semiconductor device
Shih-Ming Chang, Hsinchu (TW); and Yu-Tse Lai, Zhubei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Sep. 28, 2021, as Appl. No. 17/488,271.
Claims priority of provisional application 63/192,347, filed on May 24, 2021.
Prior Publication US 2022/0375852 A1, Nov. 24, 2022
Int. Cl. H01L 23/522 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 21/768 (2006.01); H01L 23/532 (2006.01)
CPC H01L 23/5226 (2013.01) [H01L 21/31144 (2013.01); H01L 21/32139 (2013.01); H01L 21/76816 (2013.01); H01L 21/76895 (2013.01); H01L 23/53209 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor device comprising:
forming a first conductive layer over a first interlayer dielectric (ILD) layer disposed over a substrate;
forming a second ILD layer over the first conductive layer;
forming a via in the second ILD layer to contact an upper surface of the first conductive layer;
forming a hard mask pattern over the second ILD layer;
transferring the hard mask pattern into the second ILD layer and first conductive layer, thereby forming patterned second ILD layers and patterned first wiring patterns;
after the patterning, removing the hard mask pattern; and
forming a third ILD layer between the patterned second ILD layers and the patterned first wiring patterns.