CPC H01L 23/49838 (2013.01) [H01L 23/3121 (2013.01); H01L 23/49811 (2013.01); H01L 23/49861 (2013.01)] | 17 Claims |
1. A packaged electronic device, comprising:
a power semiconductor die that comprises a first terminal and a second terminal;
a lead frame comprising a lower side and an upper side that comprises a die pad region;
a first lead and a second lead;
a dielectric substrate;
a lower metal cladding layer on a lower side of the dielectric substrate;
a first metal braze layer on an upper side of the dielectric substrate; and
a second metal braze layer is between an upper side of the lower metal cladding layer and the lower side of the dielectric substrate,
wherein the power semiconductor die is on the die pad region of the lead frame and the lead frame is on an upper side of the first metal braze layer, and
wherein the first metal braze layer is directly attached to the dielectric substrate and to the lower side of the lead frame.
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