US 12,224,222 B2
Semiconductor package having a thermally and electrically conductive spacer
Christian Neugirg, Regensburg (DE); Adrian Lis, Regensburg (DE); Peter Scherl, Regensburg (DE); and Ewald Guenther, Regenstauf (DE)
Assigned to Infineon Technologies AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on Jan. 11, 2022, as Appl. No. 17/572,858.
Prior Publication US 2023/0223312 A1, Jul. 13, 2023
Int. Cl. H01L 23/367 (2006.01); H01L 23/00 (2006.01); H01L 23/31 (2006.01); H01L 23/498 (2006.01)
CPC H01L 23/367 (2013.01) [H01L 23/3121 (2013.01); H01L 23/3171 (2013.01); H01L 23/49844 (2013.01); H01L 24/04 (2013.01); H01L 24/48 (2013.01); H01L 2224/04042 (2013.01); H01L 2224/48177 (2013.01)] 25 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a first substrate having a first metallized side;
a semiconductor die attached to the first metallized side of the first substrate at a first side of the semiconductor die, a second side of the semiconductor die opposite the first side being covered by a passivation, the passivation having a first opening that exposes at least part of a first pad at the second side of the semiconductor die;
a thermally and electrically conductive spacer attached to the part of the first pad that is exposed by the first opening in the passivation, the spacer at least partly overhanging the passivation along at least one side face of the semiconductor die;
a second substrate having a first metallized side attached to the spacer at an opposite side of the spacer as the semiconductor die; and
an encapsulant encapsulating the semiconductor die and the spacer.