US 12,224,212 B2
Semiconductor devices with backside air gap dielectric
Chun-Yuan Chen, Hsinchu (TW); Huan-Chieh Su, Changhua County (TW); Cheng-Chi Chuang, New Taipei (TW); Yu-Ming Lin, Hsinchu (TW); and Chih-Hao Wang, Hsinchu County (TW)
Assigned to Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on May 25, 2023, as Appl. No. 18/323,907.
Application 17/873,903 is a division of application No. 16/888,217, filed on May 29, 2020, granted, now 11,443,987, issued on Sep. 13, 2022.
Application 18/323,907 is a continuation of application No. 17/873,903, filed on Jul. 26, 2022, granted, now 11,664,280.
Prior Publication US 2023/0298943 A1, Sep. 21, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/8234 (2006.01); H01L 21/02 (2006.01); H01L 21/3105 (2006.01); H01L 21/764 (2006.01); H01L 23/528 (2006.01); H01L 27/088 (2006.01); H01L 29/417 (2006.01)
CPC H01L 21/823475 (2013.01) [H01L 21/02274 (2013.01); H01L 21/31053 (2013.01); H01L 21/764 (2013.01); H01L 21/823431 (2013.01); H01L 23/528 (2013.01); H01L 27/0886 (2013.01); H01L 29/41791 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure having a frontside and a backside, comprising:
an isolation structure at the backside;
one or more transistors at the frontside, the one or more transistors having source/drain epitaxial features;
two metal plugs through the isolation structure and contacting two of the source/drain epitaxial features from the backside; and
a dielectric liner filling a space between the two metal plugs, wherein the dielectric liner partially or fully surrounds an air gap between the two metal plugs.