US 12,224,210 B2
Method for FinFet fabrication and structure thereof
Han-Yu Lin, Hsinchu (TW); Yi-Ruei Jhan, Keelung (TW); Fang-Wei Lee, Hsinchu (TW); Tze-Chung Lin, Hsinchu (TW); Chao-Hsien Huang, Tainan (TW); Li-Te Lin, Hsinchu (TW); Pinyen Lin, Rochester, NY (US); and Akira Mineji, Hsinchu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on May 8, 2023, as Appl. No. 18/313,783.
Application 17/362,025 is a division of application No. 16/298,720, filed on Mar. 11, 2019, granted, now 11,056,393, issued on Jul. 6, 2021.
Application 18/313,783 is a continuation of application No. 17/362,025, filed on Jun. 29, 2021, granted, now 11,646,234.
Claims priority of provisional application 62/737,798, filed on Sep. 27, 2018.
Prior Publication US 2023/0282520 A1, Sep. 7, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/8234 (2006.01); H01L 21/02 (2006.01); H01L 21/265 (2006.01); H01L 21/3105 (2006.01); H01L 21/311 (2006.01); H01L 21/764 (2006.01); H01L 27/088 (2006.01)
CPC H01L 21/823431 (2013.01) [H01L 21/02164 (2013.01); H01L 21/0228 (2013.01); H01L 21/26586 (2013.01); H01L 21/31053 (2013.01); H01L 21/31116 (2013.01); H01L 21/764 (2013.01); H01L 21/823481 (2013.01); H01L 27/0886 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate;
a semiconductor fin protruding from the substrate, wherein the semiconductor fin has a first sidewall and a second sidewall facing away from the first sidewall;
an isolation layer disposed above the substrate, wherein the isolation layer includes a first portion disposed on the first sidewall of the semiconductor fin and a second portion disposed on the second sidewall of the semiconductor fin;
a dielectric fin, wherein a bottom portion of the dielectric fin is embedded in the second portion of the isolation layer, and wherein a top portion of the dielectric fin includes an air pocket; and
a gate structure over top and sidewall surfaces of the semiconductor fin and the dielectric fin, wherein the gate structure seals a top opening of the air pocket.