US 12,224,209 B2
Semiconductor device and manufacturing method thereof
Chia-Cheng Chao, Hsinchu (TW); Hsin-Chieh Huang, Taoyuan (TW); and Yu-Wen Wang, New Taipei (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Apr. 8, 2022, as Appl. No. 17/715,967.
Prior Publication US 2023/0326798 A1, Oct. 12, 2023
Int. Cl. H01L 21/8234 (2006.01); H01L 21/306 (2006.01); H01L 29/06 (2006.01); H01L 29/423 (2006.01)
CPC H01L 21/823412 (2013.01) [H01L 21/30604 (2013.01); H01L 21/823437 (2013.01); H01L 21/823481 (2013.01); H01L 29/0665 (2013.01); H01L 29/42392 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A manufacturing method of a semiconductor device, comprising:
forming a stack of first semiconductor layers and second semiconductor layers alternatively formed on top of one another, wherein a topmost layer of the stack is one of the second semiconductor layers;
forming a patterned mask layer on the topmost layer of the stack;
forming a trench in the stack based on the patterned mask layer to form a fin structure;
forming a cladding layer extending along sidewalls of the fin structure; and
removing the patterned mask layer and a portion of the cladding layer by performing a two-step etching process, wherein the portion of the cladding layer is removed to form cladding spacers having a concave top surface with a recess depth increasing from the sidewalls of the fin structure.