US 12,224,206 B2
Conductive structure, semiconductor structure and manufacturing method thereof
Ping-Heng Wu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Nov. 26, 2021, as Appl. No. 17/456,631.
Application 17/456,631 is a continuation of application No. PCT/CN2021/104922, filed on Jul. 7, 2021.
Claims priority of application No. 202011091938.0 (CN), filed on Oct. 13, 2020.
Prior Publication US 2022/0115295 A1, Apr. 14, 2022
Int. Cl. H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 25/065 (2023.01)
CPC H01L 21/76898 (2013.01) [H01L 23/481 (2013.01); H01L 25/0657 (2013.01); H01L 2225/06544 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a base comprising a substrate, a first dielectric layer on the substrate, and a second dielectric layer on one side of the first dielectric layer away from the substrate;
an electrical connection layer, the electrical connection layer being located in the second dielectric layer; and
a conductive structure being located in the base, wherein the conductive structure comprises:
a conductive pillar being passed through the substrate and the first dielectric layer and being electrically connected to the electrical connection layer; and
at least one embedded block being located in the substrate and in the first dielectric layer, wherein the at least one embedded block is provided at one end of the conductive pillar facing the electrical connection layer and is in contact with the conductive pillar;
wherein a coefficient of thermal expansion of the at least one embedded block is less than that of the conductive pillar; and
a distance between the at least one embedded block and the electrical connection layer is within a preset range along a direction perpendicular to the surface of the substrate, and the preset range is 5-50 nm.