US 12,224,205 B2
Semiconductor memory device and manufacturing method thereof
Jingwen Lu, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jan. 12, 2022, as Appl. No. 17/647,773.
Application 17/647,773 is a continuation of application No. PCT/CN2021/120405, filed on Sep. 24, 2021.
Claims priority of application No. 202110320833.6 (CN), filed on Mar. 25, 2021.
Prior Publication US 2022/0310447 A1, Sep. 29, 2022
Int. Cl. H01L 21/768 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H10B 12/00 (2023.01)
CPC H01L 21/76837 (2013.01) [H01L 23/5283 (2013.01); H01L 23/53266 (2013.01); H01L 23/53295 (2013.01); H10B 12/0335 (2023.02); H10B 12/31 (2023.02); H10B 12/482 (2023.02)] 18 Claims
OG exemplary drawing
 
1. A method of manufacturing a semiconductor memory device, comprising:
providing a substrate having a plurality of active areas;
forming a plurality of bit line structures on the substrate, wherein the plurality of bit line structures are sequentially provided at intervals along a first direction;
forming a dielectric layer on the substrate, wherein the dielectric layer fills up at least a gap between adjacent bit line structures;
etching the dielectric layer, to form a plurality of contact holes and a plurality of isolation structures, wherein each contact hole is between the adjacent bit line structures, the plurality of contact holes and the plurality of isolation structures are alternately provided along a second direction, the first direction is not parallel to the second direction, and a bottom of the contact hole exposes the active area;
forming an isolation layer on a side wall of each bit line structure and a side wall of each isolation structure; and
forming the isolation layer on a top of each bit line structure and a top of each isolation structure.