US 12,224,203 B2
Air gap spacer formation for nano-scale semiconductor devices
Kangguo Cheng, Schenectady, NY (US); Thomas J. Haigh, Claverack, NY (US); Juntao Li, Cohoes, NY (US); Eric G. Liniger, Sandy Hook, CT (US); Sanjay C. Mehta, Niskayuna, NY (US); Son V. Nguyen, Schenectady, NY (US); Chanro Park, Clifton Park, NY (US); and Tenko Yamashita, Schenectady, NY (US)
Assigned to Adeia Semiconductor Solutions LLC, San Jose, CA (US)
Filed by Adeia Semiconductor Solutions LLC, San Jose, CA (US)
Filed on Apr. 7, 2023, as Appl. No. 18/132,333.
Application 16/410,178 is a division of application No. 15/977,437, filed on May 11, 2018, granted, now 10,418,277, issued on Sep. 17, 2019.
Application 15/789,416 is a division of application No. 15/232,341, filed on Aug. 9, 2016, granted, now 9,892,961, issued on Feb. 13, 2018.
Application 18/132,333 is a continuation of application No. 16/410,178, filed on May 13, 2019, granted, now 11,658,062.
Application 15/977,437 is a continuation of application No. 15/789,416, filed on Oct. 20, 2017, granted, now 10,115,629, issued on Oct. 30, 2018.
Prior Publication US 2024/0079266 A1, Mar. 7, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 21/768 (2006.01); H01L 21/02 (2006.01); H01L 23/528 (2006.01); H01L 23/532 (2006.01); H01L 29/417 (2006.01); H01L 29/49 (2006.01); H01L 29/66 (2006.01); H01L 29/78 (2006.01)
CPC H01L 21/7682 (2013.01) [H01L 21/02126 (2013.01); H01L 21/02167 (2013.01); H01L 21/0217 (2013.01); H01L 21/02274 (2013.01); H01L 21/76852 (2013.01); H01L 23/528 (2013.01); H01L 23/5329 (2013.01); H01L 29/41775 (2013.01); H01L 29/4991 (2013.01); H01L 29/6653 (2013.01); H01L 29/66795 (2013.01); H01L 29/785 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a gate structure and a source/drain contact disposed adjacent to each other on a substrate;
an air gap disposed between the gate structure and the source/drain contact; and
a dielectric material disposed over the gate structure and over the air gap;
a conformal insulating liner layer comprising: (i) a first portion disposed below the air gap; (ii) a second portion disposed between the gate structure and the air gap; and (iii) a third portion disposed between the source/drain contact and the air gap, wherein:
an upper portion of the air gap is disposed above a top surface of the gate structure and below a top surface of the source/drain contact; and
a lower portion of the air gap is disposed below a bottom surface of the source/drain contact.