US 12,224,201 B2
Single crystalline silicon stack formation and bonding to a cmos wafer
Si-Woo Lee, Boise, ID (US); and Byung Yoon Kim, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Jan. 4, 2024, as Appl. No. 18/403,866.
Application 18/403,866 is a division of application No. 17/749,282, filed on May 20, 2022, granted, now 11,869,803.
Application 17/749,282 is a continuation of application No. 17/086,536, filed on Nov. 2, 2020, granted, now 11,342,218, issued on May 24, 2022.
Prior Publication US 2024/0153813 A1, May 9, 2024
Int. Cl. H01L 21/02 (2006.01); H01L 21/762 (2006.01); H01L 25/00 (2006.01); H01L 25/18 (2023.01)
CPC H01L 21/76251 (2013.01) [H01L 21/02532 (2013.01); H01L 21/02598 (2013.01); H01L 25/18 (2013.01); H01L 25/50 (2013.01); H01L 21/02381 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a layer of single crystal silicon germanium onto a surface of a silicon substrate;
epitaxially growing the silicon germanium to form a thicker single crystal silicon germanium layer;
forming a layer of single crystal silicon onto a surface of the thicker single crystal silicon germanium layer;
epitaxially growing the single crystal silicon to form a thicker single crystal silicon layer; and
forming, in repeating iterations, a number of additional layers of single crystal silicon germanium and single crystal silicon to form a vertical stack of alternating single crystal silicon and single crystal silicon germanium layers.