US 12,224,183 B2
Method of manufacturing semiconductor device
Shrane-Ning Jenq, Hsinchu County (TW); Wen-Cheng Hsu, Hsinchu County (TW); Chen-Yu Wang, Hsinchu (TW); Chih-Ming Kuo, Hsinchu County (TW); Chwan-Tyaw Chen, Hsinchu (TW); and Lung-Hua Ho, Hsinchu (TW)
Assigned to CHIPBOND TECHNOLOGY CORPORATION, Hsinchu (TW)
Filed by CHIPBOND TECHNOLOGY CORPORATION, Hsinchu (TW)
Filed on Aug. 26, 2022, as Appl. No. 17/896,171.
Prior Publication US 2023/0135424 A1, May 4, 2023
Int. Cl. H01L 21/48 (2006.01); C23C 18/54 (2006.01); C23C 28/02 (2006.01); C25D 7/12 (2006.01); H01L 21/311 (2006.01); H01L 21/3213 (2006.01); H01L 23/498 (2006.01); H01L 23/00 (2006.01)
CPC H01L 21/4857 (2013.01) [C23C 18/54 (2013.01); C23C 28/02 (2013.01); C25D 7/123 (2013.01); H01L 21/31138 (2013.01); H01L 21/32136 (2013.01); H01L 21/486 (2013.01); H01L 23/49811 (2013.01); H01L 23/49816 (2013.01); H01L 23/49838 (2013.01); H01L 23/49866 (2013.01); H01L 24/16 (2013.01); H01L 2224/16225 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A method of manufacturing semiconductor device comprising the steps of:
providing a package including a first carrier, a seed layer, a plurality of wires, a die and a molding material, the seed layer is formed on the first carrier, the plurality of wires are formed on the seed layer, the die is bonded to the plurality of wires, and the die and the plurality of wires are covered by the molding material;
disposing a second carrier on the molding material;
removing the first carrier to expose the seed layer;
removing the seed layer to expose the plurality of wires; and
depositing a gold layer on each of the plurality of wires by immersion gold plating.