US 12,224,182 B2
Fan out structure for light-emitting diode (LED) device and lighting system
Tze Yang Hin, Cupertino, CA (US); Anantharaman Vaidyanathan, San Jose, CA (US); Srini Banna, San Jose, CA (US); and Ronald Johannes Bonne, Plainfield, IL (US)
Assigned to LUMILEDS, LLC, San Jose, CA (US)
Filed by Lumileds LLC, San Jose, CA (US)
Filed on Feb. 28, 2023, as Appl. No. 18/176,222.
Application 18/176,222 is a continuation of application No. 16/750,839, filed on Jan. 23, 2020, granted, now 11,621,173.
Claims priority of provisional application 62/951,601, filed on Dec. 20, 2019.
Claims priority of provisional application 62/937,629, filed on Nov. 19, 2019.
Prior Publication US 2023/0282489 A1, Sep. 7, 2023
Int. Cl. H01L 21/48 (2006.01); F21S 41/153 (2018.01); F21V 23/00 (2015.01); F21Y 105/10 (2016.01); F21Y 105/16 (2016.01); F21Y 115/10 (2016.01); H01L 21/683 (2006.01); H01L 23/00 (2006.01); H01L 25/16 (2023.01); H01L 27/15 (2006.01); H01L 33/62 (2010.01)
CPC H01L 21/4853 (2013.01) [F21S 41/153 (2018.01); F21V 23/002 (2013.01); H01L 21/486 (2013.01); H01L 21/6835 (2013.01); H01L 24/19 (2013.01); H01L 24/81 (2013.01); H01L 24/82 (2013.01); H01L 25/167 (2013.01); H01L 27/156 (2013.01); H01L 33/62 (2013.01); F21Y 2105/10 (2016.08); F21Y 2105/16 (2016.08); F21Y 2115/10 (2016.08); H01L 2221/68345 (2013.01); H01L 2224/16225 (2013.01); H01L 2224/24225 (2013.01); H01L 2224/8112 (2013.01); H01L 2224/81192 (2013.01); H01L 2224/81815 (2013.01); H01L 2224/82815 (2013.01); H01L 2924/12041 (2013.01); H01L 2933/0041 (2013.01); H01L 2933/0066 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A lighting device, comprising:
a silicon backplane having a top surface, a bottom surface and side surfaces;
an array of metal connectors on the top surface of the silicon backplane;
an LED array on the array of metal connectors on the top surface of the silicon backplane with a spacing between adjacent LEDs in the LED array being less than 20 μm;
a substrate surrounding the side surfaces of the silicon backplane, the substrate having a top surface, a bottom surface and side surfaces; and
at least one first bond pad on the top surface of the substrate, the at least one first bond pad being electrically coupled to the array of metal connectors on the top surface of the silicon backplane.