| CPC G11C 7/1039 (2013.01) [G11C 7/08 (2013.01); G11C 7/1063 (2013.01); G11C 7/109 (2013.01)] | 19 Claims |
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1. An apparatus comprising:
a plurality of memory cell matrices including memory cells;
a plurality of sections wherein each section is included in a memory cell matrix of the plurality of memory cell matrices;
a section predecoder configured to decode a portion of row address signals and further configured to activate a section signal among a plurality of corresponding section signals responsive to the portion of row address signals;
a section selection control circuit configured to provide a plurality of sets of section sub signals based on the plurality of section signals, the plurality of sets of section sub signals including:
a set of first section sub signals including an active first section sub signal; and
a set of second section sub signals including an active second section sub signal; and
a plurality of section selection circuits corresponding to the plurality of sections,
wherein one section selection circuit among the plurality of section selection circuits is configured to activate the corresponding section responsive to the active first and second section sub signals.
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