US 12,224,030 B2
Memory system
Takahiko Sato, Yokohama (JP)
Assigned to WINDBOND ELECTRONICS CORP., Taichung (TW)
Filed by Winbond Electronics Corp., Taichung (TW)
Filed on Nov. 15, 2022, as Appl. No. 17/987,435.
Claims priority of application No. 2021-204736 (JP), filed on Dec. 17, 2021.
Prior Publication US 2023/0197184 A1, Jun. 22, 2023
Int. Cl. G11C 29/52 (2006.01); G11C 11/4093 (2006.01); G11C 11/4096 (2006.01)
CPC G11C 29/52 (2013.01) [G11C 11/4093 (2013.01); G11C 11/4096 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory system, comprising:
a memory controller; and
a semiconductor memory device;
wherein the memory controller is configured to:
send a command, an address and first check data for error detection of the command and the address to the semiconductor memory device; and
when receiving first response information indicating that no error has been detected in the command and the address from the semiconductor memory device, based on the command, send to or receive from the semiconductor memory device of data to be read from or written into the address;
wherein the semiconductor memory device is configured to:
when receiving the command, the address and the first check data from the memory controller, use the first check data to perform error detection of the command and the address, and send the first response information to the memory controller when no error is detected in the command and the address; and
when no error is detected in the command and the address, based on the command, send to or receive from the memory controller of the data to be read from or written into the address;
wherein the memory controller or the semiconductor memory device is configured to:
send the data to be read or write and second check data for error detection of the data to the other of the memory controller or the semiconductor memory device; and
the other of the memory controller or the semiconductor memory device is configured to:
when receiving the data and the second check data, use the second check data to perform error detection of the data, and send third response information indicating that no error has been detected in the data to the memory controller and the semiconductor memory device.