US 12,224,029 B2
Control method, semiconductor memory, and electronic device
Yoonjoo Eom, Hefei (CN); Lin Wang, Hefei (CN); Zhiqiang Zhang, Hefei (CN); and Yuanyuan Gong, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jan. 18, 2023, as Appl. No. 18/156,133.
Application 18/156,133 is a continuation of application No. PCT/CN2022/093935, filed on May 19, 2022.
Claims priority of application No. 202210306571.2 (CN), filed on Mar. 25, 2022; and application No. 202210501554.4 (CN), filed on May 9, 2022.
Prior Publication US 2023/0307083 A1, Sep. 28, 2023
Int. Cl. G11C 29/50 (2006.01)
CPC G11C 29/50008 (2013.01) [G11C 2029/5002 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A control method, applied to a semiconductor memory comprising a Data Mask (DM) pin, the DM pin being configured to receive an input mask signal of write data, the method comprising:
decoding a third Operand (OP) in a third Mode Register (MR) and a fourth OP in a first MR; and
in response to the semiconductor memory being in a preset test mode, controlling, in a case where the third OP meets a first decoding condition, an impedance of the DM pin to be a first value, or controlling, in a case where the third OP meets a second decoding condition, the impedance of the DM pin to be a second value according to the fourth OP,
wherein the third OP is configured to indicate whether the DM pin is a test object in the preset test mode, and the fourth OP is configured to indicate whether the DM pin is enabled.