US 12,224,028 B2
Semiconductor chip and sequence checking circuit
Shih-Cheng Kao, Hsinchu (TW); and Bi-Yang Li, Hsinchu (TW)
Assigned to GLOBAL UNICHIP CORPORATION, Hsinchu (TW); and TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by GLOBAL UNICHIP CORPORATION, Hsinchu (TW); and TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed on Jan. 30, 2023, as Appl. No. 18/161,859.
Claims priority of application No. 111130407 (TW), filed on Aug. 12, 2022.
Prior Publication US 2024/0055067 A1, Feb. 15, 2024
Int. Cl. G11C 29/50 (2006.01)
CPC G11C 29/50004 (2013.01) [G11C 29/50012 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor chip, including:
a physical layer, including at least one sequence checking circuit and at least one signal transmission path, wherein the at least one sequence checking circuit is configured to generate at least one test result signal according to a clock signal and at least one test data signal transmitted through the at least one signal transmission path, and the clock signal is not transmitted through the at least one signal transmission path; and
a processing circuit, electrically coupled to the physical layer and configured to determine an operation status of the at least one signal transmission path according to the voltage level of the at least one test result signal.