CPC G11C 29/42 (2013.01) [G11C 29/18 (2013.01); G11C 29/46 (2013.01)] | 27 Claims |
1. A semiconductor memory device comprising:
a command address control circuit configured to generate, in response to an external control signal, an error correction command and a selection address for executing an error correction operation;
an error flag generation circuit configured to execute the error correction operation by correcting an error of data corresponding to the selection address and configured to generate a target error flag based on a predetermined pattern of the error that occurred previously in the error correction operation and which is indicative of a problem in an operation of the semiconductor memory device; and
an error information processing circuit configured to generate, based on the target error flag, a target address that is used as the selection address for a target error correction operation that is executed when the error correction operation is executed a predetermined number of times.
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