US 12,224,026 B2
Semiconductor memory device and memory system performing error correction operation
Hong Ki Moon, Gyeonggi-do (KR)
Assigned to SK hynix Inc., Gyeonggi-do (KR)
Filed by SK hynix Inc., Gyeonggi-do (KR)
Filed on Jan. 25, 2023, as Appl. No. 18/101,123.
Claims priority of application No. 10-2022-0149835 (KR), filed on Nov. 10, 2022.
Prior Publication US 2024/0161853 A1, May 16, 2024
Int. Cl. G11C 29/00 (2006.01); G11C 29/18 (2006.01); G11C 29/42 (2006.01); G11C 29/46 (2006.01)
CPC G11C 29/42 (2013.01) [G11C 29/18 (2013.01); G11C 29/46 (2013.01)] 27 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a command address control circuit configured to generate, in response to an external control signal, an error correction command and a selection address for executing an error correction operation;
an error flag generation circuit configured to execute the error correction operation by correcting an error of data corresponding to the selection address and configured to generate a target error flag based on a predetermined pattern of the error that occurred previously in the error correction operation and which is indicative of a problem in an operation of the semiconductor memory device; and
an error information processing circuit configured to generate, based on the target error flag, a target address that is used as the selection address for a target error correction operation that is executed when the error correction operation is executed a predetermined number of times.