| CPC G11C 17/18 (2013.01) [G11C 17/16 (2013.01)] | 19 Claims |
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1. A non-volatile memory device, comprising:
a memory cell array comprising a plurality of memory cells; and
a sense amplifier configured to read data of the plurality of memory cells and output the read data,
wherein the sense amplifier comprises:
a first stage sense amplifier configured to sense a voltage difference between a reference voltage and a voltage of a bit line connected to at least one memory cell among the plurality of memory cells, and perform a primary amplification of the sensed voltage difference; and
a second stage sense amplifier configured to perform a secondary amplification of a first result of the primary amplification and output a second result of the secondary amplification,
wherein the first stage sense amplifier comprises a first positive feedback circuit connected to a first input terminal to which the voltage of the bit line is applied and a second input terminal to which the reference voltage is applied,
wherein the second stage sense amplifier comprises a second positive feedback circuit connected to a first output terminal and a second output terminal, which output the second result of the secondary amplification, and
wherein a first input terminal of the second stage sense amplifier and a second input terminal of the second stage sense amplifier are connected to the first input terminal of the first stage sense amplifier and the second input terminal of the first stage sense amplifier, respectively,
wherein the first input terminal is connected to the bit line connected to at least one memory cell among the plurality of memory cells, and
wherein a first reference resistance element and a first reference PMOS transistor are connected to the bit line between the at least one memory cell and the first input terminal.
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