CPC G11C 17/18 (2013.01) [G11C 17/02 (2013.01); G11C 17/16 (2013.01); H10B 20/25 (2023.02)] | 20 Claims |
1. A magnetoresistive random access memory (MRAM) comprising:
an MRAM array including MRAM cells arranged in rows and columns, each MRAM cell of the MRAM array including a corresponding Magnetic Tunnel Junction (MTJ) which includes a corresponding tunnel dielectric layer, wherein the corresponding MTJ is capable of being in a blown state or non-blown state, in which, in the non-blown state, the corresponding MTJ is capable of being in a high resistive state (HRS) or a low resistive state (LRS), the LRS corresponding to a lower resistance than the HRS, and the blown state corresponding to a permanent breakdown of the corresponding tunnel dielectric layer which results in a lower resistance than the LRS;
write circuitry configured to perform a one-time-programmable (OTP) write operation to blow selected MRAM cells of the MRAM array, wherein, for each MRAM cell being blown, the write circuitry is configured to:
use an initial OTP program reference for the MRAM cell being blown to detect onset of tunnel dielectric breakdown after application of each OTP write pulse of the OTP write operation; and
after detection of the onset, update the initial OTP program reference to obtain an updated OTP program reference, apply at least one additional OTP write pulse to the MRAM cell being blown, and use the updated OTP program reference to verify that current saturation of the MRAM cell being blown has occurred.
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