US 12,224,020 B2
Semiconductor storage device and memory system
Kenro Kikuchi, Fujisawa Kanagawa (JP); Masahiko Iga, Yokohama Kanagawa (JP); and Nobushi Matsuura, Kamakura Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Sep. 2, 2022, as Appl. No. 17/902,754.
Claims priority of application No. 2022-041744 (JP), filed on Mar. 16, 2022.
Prior Publication US 2023/0317181 A1, Oct. 5, 2023
Int. Cl. G11C 16/16 (2006.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/3445 (2013.01) [G11C 16/08 (2013.01); G11C 16/16 (2013.01); G11C 16/24 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor storage device comprising:
a first memory block constituted with a plurality of first strings each including a first select transistor, a plurality of first memory cell transistors, and a second select transistor in this order;
a second memory block constituted with a plurality of second strings each including a third select transistor, a plurality of second memory cell transistors, and a fourth select transistor in this order;
a control circuit configured to perform an erase operation on the first memory block and the second memory block;
a first bit line connected to one end portion of one string of the plurality of first strings; and
a second bit line connected to one end portion of one string of the plurality of second strings,
wherein:
when the first memory block is an open block including a memory cell transistor having a threshold of an erase level and the second memory block is a closed block not including the memory cell transistor having the threshold of the erase level, the control circuit changes setting of a first erase-verify operation that is an erase-verify operation included in the erase operation on the first memory block and setting of a second erase-verify operation that is a erase-verify operation included in the erase operation on the second memory block, and
a magnitude of a first cell current that flows through the first bit line upon the first erase-verify operation is smaller than a magnitude of a second cell current that flows through the second bit line upon the second erase-verify operation.