US 12,224,019 B2
Cache processes with adaptive dynamic start voltage calculation for memory devices
Xiang Yang, Santa Clara, CA (US); Ali Khakifirooz, Brookline, MA (US); Pranav Kalavade, San Jose, CA (US); and Shantanu R. Rajwade, Sunnyvale, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 25, 2021, as Appl. No. 17/213,150.
Prior Publication US 2022/0310178 A1, Sep. 29, 2022
Int. Cl. G11C 16/00 (2006.01); G11C 7/10 (2006.01); G11C 16/10 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01); G11C 16/30 (2006.01); G11C 16/34 (2006.01)
CPC G11C 16/3436 (2013.01) [G11C 7/1048 (2013.01); G11C 16/102 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/30 (2013.01); G11C 16/3404 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory chip controller of a flash memory device, the memory chip controller including processing circuitry to:
receive data for a first page of N pages of data;
receive data for subsequent pages of the N pages of data;
for a page number p of the N pages, and for cells of a memory location of the device, wherein the cells are to be programmed to a nth threshold voltage level Ln, Ln associated with a program verify voltage level PVn:
apply a pulse voltage to at least some of the cells;
sample a fraction of said at least some of the cells for PVn verify:
in response to a determination that a number of sampled cells that pass PVn verify is equal to or above a pre-specified threshold, determine a dynamic start voltage (DSV) to be equal to said pulse voltage; and
program the cells of the memory location of the device to the nth threshold voltage level Ln including:
programming the cells based on the data for the first page while receiving the data for subsequent pages of the N pages; and
programming the cells based on the data for the subsequent pages, wherein programming the cells further includes, for at least n=1 and for the page number p, causing the DSV to be applied to the cells.