US 12,224,018 B2
Semiconductor storage device and voltage control method for semiconductor storage device
Xu Li, Yokohama (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Mar. 10, 2022, as Appl. No. 17/654,292.
Claims priority of application No. 2021-153543 (JP), filed on Sep. 21, 2021.
Prior Publication US 2023/0093270 A1, Mar. 23, 2023
Int. Cl. G11C 16/30 (2006.01); G11C 5/14 (2006.01); G11C 8/12 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01); G11C 16/34 (2006.01); G11C 8/08 (2006.01); G11C 16/32 (2006.01)
CPC G11C 16/30 (2013.01) [G11C 5/147 (2013.01); G11C 8/12 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/10 (2013.01); G11C 16/26 (2013.01); G11C 16/3459 (2013.01); G11C 8/08 (2013.01); G11C 16/32 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A semiconductor storage device comprising:
a first block including a first memory cell;
a second block including a second memory cell;
a first local word line connected to a gate of the first memory cell;
a second local word line connected to a gate of the second memory cell;
a bit line electrically connected to one end of the first memory cell;
a global word line;
a voltage generation circuit configured to generate and supply a read voltage to the global word line;
a first transfer transistor connected between the global word line and the first local word line;
a second transfer transistor connected between the global word line and the second local word line;
a first block decoder configured to supply either one of a first selection signal or a first non-selection signal to a gate of the first transfer transistor in response to a block address input thereto;
a second block decoder configured to supply either one of a second selection signal or a second non-selection signal to a gate of the second transfer transistor in response to the block address input thereto; and
a control unit configured to perform a read operation to either one of the first memory cell or the second memory cell in response to a read command accompanied with the block address, wherein
the voltage generation circuit is further configured to generate and supply a first power voltage and a second power voltage to each of the first block decoder and the second block decoder, and
during the read operation, a value of the first power voltage is changed between a first set value and a second set value lower than the first set value, and a value of the second power voltage is changed between a third set value lower than the first set value and a fourth set value lower than both of the second set value and the third set value, the first set value being larger than zero volt, the fourth set value being lower than zero volt.