US 12,224,017 B2
Read level compensation for partially programmed blocks of memory devices
Nagendra Prasad Ganesh Rao, Folsom, CA (US); Paing Z. Htet, Union City, CA (US); Sead Zildzic, Jr., Folsom, CA (US); Thomas Fiala, Folsom, CA (US); Jian Huang, Union City, CA (US); and Zhenming Zhou, San Jose, CA (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Sep. 12, 2022, as Appl. No. 17/942,977.
Prior Publication US 2024/0087655 A1, Mar. 14, 2024
Int. Cl. G11C 16/30 (2006.01); G11C 16/08 (2006.01); G11C 16/16 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/26 (2013.01) [G11C 16/08 (2013.01); G11C 16/16 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a memory device comprising a plurality of blocks, each block of the plurality of blocks comprising a plurality of wordlines, each wordline of the plurality of wordlines connected to a respective set of memory cells; and
a processing device, operatively coupled with the memory device to perform operations comprising:
responsive to receiving a read request that specifies a block, determining a value of a metric reflective of a number of programmed wordlines of the block;
responsive to determining, based on the value of the metric, that the block is in a partially programmed state, identifying a read voltage offset corresponding to the value of the metric; and
performing, using the read voltage offset, a read operation responsive to the read request.