US 12,224,015 B2
Staggered active bitline sensing
Ali Khakifirooz, Brookline, MA (US); Rezaul Haque, El Dorado Hills, CA (US); Dhanashree Kulkarni, El Dorado Hills, CA (US); and Bayan Nasri, Folsom, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Apr. 21, 2021, as Appl. No. 17/236,651.
Prior Publication US 2022/0343982 A1, Oct. 27, 2022
Int. Cl. G11C 16/24 (2006.01); G11C 16/04 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/24 (2013.01) [G11C 16/0483 (2013.01); G11C 16/26 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory chip controller comprising:
one or more substrates; and
logic coupled to the one or more substrates, wherein the logic is at least partly implemented in one or more of configurable or fixed-functionality hardware, and the logic coupled to the one or more substrates is to:
apply a first set of control signals to even bitlines in NAND memory, wherein the first set of control signals are to include an even pre-charge signal that is shared by even pre-charge transistors;
sense voltage levels of the even bitlines during an even sensing time period;
apply a second set of control signals to odd bitlines in the NAND memory; and
sense voltage levels of the odd bitlines during an odd sensing time period, wherein the second set of control signals are applied after expiration of a stagger time period between the even sensing time period and the odd sensing time period, and wherein the even pre-charge signal activates the even pre-charge transistors from a deactivated state during the stagger time period.