CPC G11C 16/24 (2013.01) [G11C 16/0483 (2013.01); G11C 16/26 (2013.01)] | 20 Claims |
1. A memory chip controller comprising:
one or more substrates; and
logic coupled to the one or more substrates, wherein the logic is at least partly implemented in one or more of configurable or fixed-functionality hardware, and the logic coupled to the one or more substrates is to:
apply a first set of control signals to even bitlines in NAND memory, wherein the first set of control signals are to include an even pre-charge signal that is shared by even pre-charge transistors;
sense voltage levels of the even bitlines during an even sensing time period;
apply a second set of control signals to odd bitlines in the NAND memory; and
sense voltage levels of the odd bitlines during an odd sensing time period, wherein the second set of control signals are applied after expiration of a stagger time period between the even sensing time period and the odd sensing time period, and wherein the even pre-charge signal activates the even pre-charge transistors from a deactivated state during the stagger time period.
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