| CPC G11C 16/16 (2013.01) [G11C 16/102 (2013.01); G11C 16/26 (2013.01); G06F 2212/7205 (2013.01)] | 18 Claims |
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1. An apparatus comprising:
one or more control circuits configured to connect to a three-dimensional memory structure comprising a plurality of erase blocks, each erase block comprising physical pages of memory cells, wherein the one or more control circuits are configured to:
read first valid data from one or more source erase blocks that store data at n bits per memory cell, wherein n is a positive integer greater than 1;
program the first valid data as m bits per memory cell in a plurality of physical pages of memory cells in a destination erase block, wherein m is a positive integer less than n;
read second valid data from the one or more source erase blocks;
transfer the first valid data, physical page-by-physical page, from the plurality of physical pages of memory cells in the destination erase block to first data latches associated with the destination erase block;
transfer the second valid data, physical page-by-physical page, to second data latches associated with the destination erase block; and
program the second valid data into the plurality of the physical pages of memory cells in the destination erase block physical page-by-physical page based on contents of the first data latches and the second data latches after programming the first valid data into the plurality of the physical pages such that the memory cells in the plurality of the physical pages in the destination erase block each store n bits per memory cell.
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