US 12,224,013 B2
Semiconductor memory device
Jae Woong Kim, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Mar. 13, 2023, as Appl. No. 18/183,008.
Claims priority of application No. 10-2022-0116545 (KR), filed on Sep. 15, 2022.
Prior Publication US 2024/0096421 A1, Mar. 21, 2024
Int. Cl. G11C 16/24 (2006.01); G11C 16/08 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/102 (2013.01) [G11C 16/08 (2013.01); G11C 16/26 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A semiconductor memory device, comprising:
a memory cell array comprising a cell string and an auxiliary string, which are coupled to each other through a channel layer that is coupled to a bit line, wherein the cell string comprises a plurality of memory cells stacked along a first side portion of the channel layer and wherein the auxiliary string comprises a plurality of auxiliary transistors stacked along a second side portion of the channel layer; and
a voltage supply circuit configured to apply a first pass voltage to an unselected auxiliary word line among a plurality of auxiliary word lines coupled to the plurality of auxiliary transistors and, apply a first voltage, which is less than the first pass voltage, to an unselected word line among the plurality of word lines coupled to the plurality of memory cells while applying a program voltage or a read voltage to the selected word line among the plurality of word lines.