US 12,224,012 B2
All level coarse/fine programming of memory cells
Lawrence Celso Miranda, San Jose, CA (US); Tomoko Ogura Iwasaki, San Jose, CA (US); Sheyang Ning, San Jose, CA (US); and Jeffrey S. McNeil, Nampa, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 29, 2023, as Appl. No. 18/127,768.
Claims priority of provisional application 63/327,611, filed on Apr. 5, 2022.
Prior Publication US 2023/0317171 A1, Oct. 5, 2023
Int. Cl. G11C 16/10 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/10 (2013.01) [G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system, comprising:
a memory array comprising a plurality of memory cells electrically coupled to a plurality of wordlines and a plurality of bitlines; and
a controller coupled to the memory array, the controller to perform operations comprising:
identifying a set of memory cells for performing a memory programming operation, wherein the memory cells are electrically coupled to a target wordline and a set of target bitlines;
causing a first voltage to be applied to the target wordline, wherein the first voltage is incremented every time period over a number of time periods that corresponds to a number of threshold voltages to be programmed;
causing a second voltage to be applied to a first bitline over the number of time periods;
causing a third voltage to be applied to a second bitline, wherein the third voltage is incremented during a second time period of the number of time periods, wherein the second time period follows a first time period;
causing a fourth voltage to be applied to a third bitline, wherein the fourth voltage is incremented during a third time period of the number of time periods, wherein the third time period follows the second time period; and
causing a fifth voltage to be applied to a fourth bitline over the number of time periods.