US 12,224,010 B2
Non-volatile memory
Seiji Takenaka, Kyoto (JP)
Assigned to Rohm Co., Ltd., Kyoto (JP)
Appl. No. 18/021,606
Filed by ROHM CO., LTD., Kyoto (JP)
PCT Filed Aug. 5, 2021, PCT No. PCT/JP2021/029134
§ 371(c)(1), (2) Date Feb. 16, 2023,
PCT Pub. No. WO2022/059378, PCT Pub. Date Mar. 24, 2022.
Claims priority of application No. 2020-156967 (JP), filed on Sep. 18, 2020.
Prior Publication US 2023/0307049 A1, Sep. 28, 2023
Int. Cl. G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/26 (2006.01)
CPC G11C 16/0441 (2013.01) [G11C 16/10 (2013.01); G11C 16/26 (2013.01)] 10 Claims
OG exemplary drawing
 
1. A non-volatile memory, comprising:
a first transistor;
a second transistor having a gate connected to a gate of the first transistor;
a resistor having a first terminal and a second terminal, the first terminal being connected to a source of the first transistor;
a read voltage feed circuit configured to feed a read voltage for turning on at least one of the first and second transistors to between the gate of the first transistor and the second terminal of the resistor and to between the gate and a source of the second transistor; and
a signal output circuit configured to output, in a read operation in which the read voltage feed circuit feeds the read voltage, a signal associated with a first value or a signal associated with a second value based on drain currents of the first and second transistors.