US 12,224,006 B2
High-speed and large-current adjustable pulse circuit, operating circuit and operating method of phase-change memory
Xingsheng Wang, Hubei (CN); Yinghao Ma, Hubei (CN); Fan Yang, Hubei (CN); Chengxu Wang, Hubei (CN); Menghua Huang, Hubei (CN); and Xiangshui Miao, Hubei (CN)
Assigned to HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY, Hubei (CN)
Appl. No. 18/031,356
Filed by HUAZHONG UNIVERSITY OF SCIENCE AND TECHNOLOGY, Hubei (CN)
PCT Filed Jul. 7, 2022, PCT No. PCT/CN2022/104246
§ 371(c)(1), (2) Date Apr. 12, 2023,
PCT Pub. No. WO2023/236304, PCT Pub. Date Dec. 14, 2023.
Claims priority of application No. 202210650106.0 (CN), filed on Jun. 9, 2022.
Prior Publication US 2024/0371438 A1, Nov. 7, 2024
Int. Cl. G11C 11/00 (2006.01); G11C 13/00 (2006.01)
CPC G11C 13/0038 (2013.01) [G11C 13/0004 (2013.01); G11C 13/0069 (2013.01); G11C 2013/0078 (2013.01)] 13 Claims
OG exemplary drawing
 
1. A high-speed and large-current adjustable pulse circuit, comprising a clamping structure, a current mirror structure, and a leakage current shutdown structure, wherein
the clamping structure comprises a clamping operational amplifier and a first MOS transistor, a non-inverting input terminal of the clamping operational amplifier is configured to connect to a control pulse voltage, an inverting input terminal of the clamping operational amplifier is grounded through a reference resistor, and an output terminal of the clamping operational amplifier is connected to a gate of the first MOS transistor, a source terminal of the first MOS transistor is connected to the inverting input terminal of the clamping operational amplifier;
the current mirror structure comprises a second MOS transistor, a third MOS transistor, a fourth MOS transistor, and a fifth MOS transistor, wherein a source terminal of the fourth MOS transistor is connected to a voltage source, a drain terminal of the fourth MOS transistor is connected to a source terminal of the second MOS transistor, a drain terminal of the second MOS transistor is connected to a drain terminal of the first MOS transistor, a gate of the second MOS transistor is connected to the drain terminal of the second MOS transistor, a gate of the fourth MOS transistor is connected to the drain terminal of the fourth MOS transistor, a source terminal of the fifth MOS transistor is connected to the voltage source, and a drain terminal of the fifth MOS transistor is connected to a source terminal of the third MOS transistor, a drain terminal of the third MOS transistor serves as an output terminal of the high-speed and large-current adjustable pulse circuit, the gate of the second MOS transistor is connected to a gate of the third MOS transistor, and the gate of the fourth MOS transistor is connected to a gate of the fifth MOS transistor;
the leakage current shutdown structure comprises a sixth MOS transistor, a seventh MOS transistor and a buffer, wherein gates of the sixth MOS transistor and the seventh MOS transistor are respectively connected to the control pulse voltage through the buffer, the gate of the fifth MOS transistor is connected to the voltage source through the sixth MOS transistor, the gate of the third MOS transistor is connected to the voltage source through the seventh MOS transistor, wherein the buffer is configured to output a shutdown voltage for turning off the sixth MOS transistor and the seventh MOS transistor when a control pulse occurs, and the buffer is configured to output a turn-on voltage for turning on the sixth MOS transistor and the seventh MOS transistor when the control pulse does not occur.