US 12,224,005 B1
Lifetime mixed level non-volatile memory system
G. R. Mohan Rao, Allen, TX (US)
Assigned to Vervain, LLC, Plano, TX (US)
Filed by Vervain, LLC, Plano, TX (US)
Filed on Oct. 25, 2024, as Appl. No. 18/926,560.
Application 14/525,411 is a division of application No. 13/455,267, filed on Apr. 25, 2012, granted, now 8,891,298, issued on Nov. 18, 2014.
Application 18/926,560 is a continuation of application No. 18/893,328, filed on Sep. 23, 2024.
Application 18/893,328 is a continuation of application No. 18/613,466, filed on Mar. 22, 2024, granted, now 12,119,054, issued on Oct. 15, 2024.
Application 18/613,466 is a continuation of application No. 18/390,193, filed on Dec. 20, 2023, granted, now 11,967,370, issued on Apr. 23, 2024.
Application 18/390,193 is a continuation of application No. 18/387,546, filed on Nov. 7, 2023, granted, now 11,967,369, issued on Apr. 23, 2024.
Application 18/387,546 is a continuation of application No. 17/203,385, filed on Mar. 16, 2021, granted, now 11,830,546, issued on Nov. 28, 2023.
Application 17/203,385 is a continuation of application No. 16/006,299, filed on Jun. 12, 2018, granted, now 10,950,300, issued on Mar. 16, 2021.
Application 16/006,299 is a continuation of application No. 14/950,553, filed on Nov. 24, 2015, granted, now 9,997,240, issued on Jun. 12, 2018.
Application 14/950,553 is a continuation of application No. 14/525,411, filed on Oct. 28, 2014, granted, now 9,196,385, issued on Nov. 24, 2015.
Claims priority of provisional application 61/509,257, filed on Jul. 19, 2011.
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 11/56 (2006.01); G06F 11/10 (2006.01); G06F 12/02 (2006.01); G11C 16/16 (2006.01); G11C 16/34 (2006.01); G11C 29/00 (2006.01); G11C 29/52 (2006.01)
CPC G11C 11/5635 (2013.01) [G06F 11/1068 (2013.01); G06F 11/1072 (2013.01); G06F 12/0246 (2013.01); G11C 11/5621 (2013.01); G11C 11/5678 (2013.01); G11C 16/16 (2013.01); G11C 16/3495 (2013.01); G11C 29/52 (2013.01); G11C 29/76 (2013.01); G06F 2212/7202 (2013.01); G11C 2211/5641 (2013.01)] 18 Claims
OG exemplary drawing
 
1. An apparatus for storing data in a nonvolatile memory, the apparatus comprising:
[a] a controller configured to erase a group of physical memory cells in the nonvolatile memory;
[b] the controller configured to write multiple bits of information to each of a first group of physical memory cells in the nonvolatile memory;
[c] the controller configured to map a logical address range to a physical address range for the first group of physical memory cells in the nonvolatile memory;
[d] the controller configured to determine if the first group of physical memory cells fails a data integrity test;
[e] if the first group of physical memory cells fails the data integrity test, the controller writes at least some of the information stored in the first group of physical memory cells to a second group of physical memory cells in the nonvolatile memory, the controller writing a single bit of information per cell in the second group of physical memory cells; and
[f] the controller configured to map the logical address range to a second physical address range for the second group of physical memory cells.