US 12,224,004 B2
Memory device, memory system, and method of operating the same
Weijun Wan, Wuhan (CN); and Yue Sheng, Wuhan (CN)
Assigned to YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed by YANGTZE MEMORY TECHNOLOGIES CO., LTD., Wuhan (CN)
Filed on Dec. 14, 2022, as Appl. No. 18/081,065.
Application 18/081,065 is a continuation of application No. PCT/CN2022/132854, filed on Nov. 18, 2022.
Claims priority of application No. 202210028189.X (CN), filed on Jan. 11, 2022.
Prior Publication US 2023/0223078 A1, Jul. 13, 2023
Int. Cl. G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/10 (2006.01); G11C 16/24 (2006.01); G11C 16/34 (2006.01)
CPC G11C 11/5628 (2013.01) [G11C 11/5671 (2013.01); G11C 16/0483 (2013.01); G11C 16/10 (2013.01); G11C 16/24 (2013.01); G11C 16/3459 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a memory cell array, wherein the memory cells in the memory cell array are arranged in rows and columns, and each memory cell is set to one of 2N levels corresponding to a piece of N-bits data, where N is an integer greater than 1; and
a peripheral circuit coupled to the memory cell array and configured to:
perform first programming and second programming sequentially and respectively on the memory cell array in a first physical page and a second physical page in a cache programming manner, and
program at least a selected row of the memory cells based on N logical pages of the first physical page and the second physical page during the first programming and the second programming,
wherein the peripheral circuit comprises page buffers respectively coupled to bit lines, each page buffer comprising:
a bias latch, (N−1) data latches, and a cache latch coupled to a data path,
the bias latch is configured to store second non-physical page information, and the (N−1) data latches and the cache latch are configured to, during a process of programming to the N logical pages of the first physical page and the second physical page, function as N page latches to temporarily store programming data to be written into the N logical pages;
wherein the peripheral circuit is further configured to:
in the process of programming the first physical page, disable a bit line bias function to release the bias latch to replace one of the N page latches to perform a programming verification of memory states;
release one of the N page latches to cache program data of one of the N logical pages of the second physical page; and
in the process of programming the first physical page, store the program data of the one of the N logical pages of the second physical page in a released page latch.