US 12,224,003 B2
Ferroelectric-based synaptic device and method of operating the synaptic device, and 3D synaptic device stack using the synaptic devices
Jong-Ho Lee, Seoul (KR); and Jeong-Hyun Kim, Seoul (KR)
Assigned to SEOUL NATIONAL UNIVERSITY R&DB FOUNDATION, Seoul (KR)
Filed by Seoul National University R&DB FOUNDATION, Seoul (KR)
Filed on Mar. 3, 2023, as Appl. No. 18/117,108.
Claims priority of provisional application 63/316,626, filed on Mar. 4, 2022.
Prior Publication US 2023/0282275 A1, Sep. 7, 2023
Int. Cl. G11C 11/54 (2006.01); G11C 11/22 (2006.01); H10B 43/30 (2023.01); H10B 53/30 (2023.01)
CPC G11C 11/54 (2013.01) [G11C 11/221 (2013.01); H10B 43/30 (2023.02); H10B 53/30 (2023.02)] 14 Claims
OG exemplary drawing
 
1. A ferroelectric-based synaptic device having a source, a drain, a semiconductor body in which a channel region is formed, a gate electrode, and an insulating layer stack disposed between the semiconductor body and the gate electrode,
wherein the insulating layer stack includes:
a charge trap layer made of a material capable of storing or trapping charges and disposed on the channel region of the semiconductor body;
a ferroelectric layer made of a ferroelectric material; and
an insulating layer disposed between the charge trap layer and the ferroelectric layer, and
wherein weight information of the ferroelectric-based synaptic device is temporarily stored in the charge trap layer and non-volatilely stored in the ferroelectric layer, and
wherein the insulating layer stack does not include a tunneling insulating layer between the channel of the semiconductor body and the charge trap layer.